1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a memory cell circuit and a control circuit that is used during a write operation.
2. Description of the Related Art
Conventionally, there is a known semiconductor memory device in which an access transistor is provided between a memory node of a memory cell and a bit line, and the access transistor is controlled using a word line (see Japanese Unexamined Patent Application Publication No. H02-094196 and U.S. Pat. No. 7,313,021).
There is also a known technique in which a path between a P-channel MOS transistor of a memory cell and a memory node is interrupted so as to expand a write voltage operation range of an SRAM (Static Random Access Memory) (see U.S. Pat. No. 7,286,390).